1. Field of the Invention
The present invention relates to a memory device mounted in a semiconductor integrated circuit.
2. Description of the Related Art
In recent years, a voltage ID (VID) that allows a power supply voltage to be supplied in accordance with chip performance has been adopted for system LSIs in order to reduce current consumption and to improve LSI performance.
For example, an application-specific integrated circuit (ASIC) core is a region in a system LSI for which VID is adopted. However, a chip includes regions such as an input/output (I/O) circuit and other analog blocks for which power supply voltage standards are specified and for which the power supply voltage is not adjusted using VID. Hence, the chip includes a mixture of regions for which the power supply voltage is adjusted using VID and which use various power supply voltages and regions for which the power supply voltage is not adjusted using VID and for which the power supply voltage is fixed.
Furthermore, the phase of a clock or an operating frequency may vary among regions that use different power supply voltages. Thus, when data is transmitted and received between regions that use different power supply voltages, a phase shift in the clock or a difference in operating frequency is corrected so that data is transmitted and received with different clocks and operating frequencies used for the regions that use different power supply voltages. To achieve this, a memory device with a plurality of asynchronous ports is used (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2008-47180). That is, when transmitted from one region, data is temporarily stored in a memory device, and another region reads the data from the memory device.
The memory device conventionally operates using a single power supply voltage. Thus, the following configuration is required: the memory device is located in one of the regions that use different power supply voltage, and the regions are connected together by a level conversion circuit or a buffer circuit at the boundary between the regions.
In this case, timings for transmitting and receiving signals for a setup time, a hold time, and the like input to the region that uses the fixed power supply voltage are varied by the power supply voltage for the region for which the power supply voltage varies. Thus, the power supply voltage for the region for which the power supply voltage varies needs to be taken into account for timings for transmitting and receiving the signals to and from the region that uses the fixed power supply voltage.
As described above, the power supply voltages for the respective regions need to be taken into account in analyzing the timings for transmitting and receiving the signals. Hence, the analysis is disadvantageously complicated.
Moreover, all the power supply voltages used for the regions for which the power supply voltage is adjusted using VID need to be taken into account. This disadvantageously contributes to reducing the margins of the timings at which the respective regions transmit and receive the signals.